1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to patterning low-k dielectrics used in metallization layers by means of sophisticated lithography with appropriate ARC layers.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing the performance of these circuits in terms of speed and/or power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip.
In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements is further decreased, and has now even reached 0.05 μm and less, it turns out, however, that the signal propagation delay is no longer limited by the field effect transistors but is limited, owing to the increased circuit density, by the close proximity of the interconnect lines, since the line-to-line capacitance (C) is increased in combination with an increased resistance (R) of the lines due to their reduced cross-sectional area. The parasitic RC time constants therefore require the introduction of a new type of material for forming the metallization layer.
Traditionally, metallization layers are formed in a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities than may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by copper or copper alloys, which have a significantly lower electrical resistance and a higher resistivity against electromigration. For devices having feature sizes of 0.09 μm and less, it turns out that simply replacing aluminum by copper-based metals does not provide the required decrease of the parasitic RC time constants, and therefore the well established and well known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>5) are increasingly replaced by so-called low-k dielectric materials having a relative permittivity of less than 3.1. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a low-k dielectric/copper-based metallization layer is associated with a plurality of problems that need to be addressed.
For example, copper may not be deposited in relatively high amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not efficiently be patterned by well-established anisotropic etch processes. Therefore, the so-called damascene technique is frequently employed in forming metallization layers including copper lines. Typically, in the damascene technique, the dielectric layer is deposited and then patterned with trenches and vias that are subsequently filled with copper by plating methods, such as electroplating or electroless plating. Although the damascene technique is presently a well-established technique for forming copper-based metallization layers in standard dielectric materials, such as silicon dioxide, the employment of low-k dielectrics, however, requires the development of new dielectric diffusion barrier layers to avoid copper contamination of adjacent material layers, as copper may readily diffuse in a variety of dielectric materials. Although silicon nitride is known as an effective copper diffusion barrier, silicon nitride may not be considered as an option in low-k dielectric layer stacks owing to its high permittivity. Therefore, presently, silicon carbide is deemed as a viable candidate for a copper diffusion barrier. It turns out, however, that copper's resistance against electromigration strongly depends on the interface between the copper and the adjacent diffusion barrier layer. Therefore, in sophisticated integrated circuits featuring high current densities, it is generally preferable to use up to 20% nitrogen in the silicon carbide layer, thereby remarkably reducing the electromigration of copper as compared to the electromigration that occurs in pure silicon carbide.
A further problem in forming low-k copper-based metallization layers has been under-estimated in the past and is now considered a major challenge in the integration of low-k dielectrics. During the patterning of the low-k dielectric material, advanced photolithography is required to image the structure, including vias and/or trenches, into the photo-resist that is sensitive in the deep UV range. In developing the photoresist, certain portions of the resist, which have been exposed, may however not be completely removed as required and thus the structure may then not be correctly transferred into the underlying low-k dielectric material during the subsequent etch process. The effect of insufficiently exposing and developing the photoresist is also referred to as resist poisoning. It is believed that a significant change of the resist sensitivity may be caused by an interaction of nitrogen and nitrogen radicals with the resist layer, thereby locally blocking the photo acidic generator effect during exposure and post-exposure bake of the resist and thus locally modifying the resist structure after resist development (footing). The problem is becoming even more important as the wavelength of the lithography used is reduced as a consequence of more sophisticated process requirements. For instance, currently the patterning of critical features sizes of cutting edge devices may be performed on the basis of a 193 nm (nanometer) light source, requiring appropriately designed photoresists that are highly sensitive in this wavelength range. It turns out, however, that with increased sensitivity at shorter wavelengths, the available photoresists also exhibit an increased sensitivity for resist poisoning mechanisms. Since the introduction of the 90 nm technology may also require a correspondingly advanced lithography in the formation of a metallization layer contacting the circuit elements, increased problems may occur during the patterning of the low-k dielectric as nitrogen and/or compounds may readily be present within the low-k material and other layers in the layer stack, which then may interact with the resist exhibiting the increased sensitivity to resist poisoning. With reference to FIGS. 1a-1c, a typical conventional process flow will now be described to explain the problems involved in patterning a metallization layer by advanced photolithography in more detail.
FIG. 1a schematically shows a cross-sectional view of a typical conventional semi-conductor device 100 in which a low-k dielectric material layer 106 is to be patterned by means of an advanced photolithography in which, for instance, a 193 nm light source is used. The semiconductor device 100 comprises a substrate 101, which may have formed thereon one or more circuit elements that may, in sophisticated devices, have critical dimensions of 0.1 μm and significantly less. For convenience, a corresponding circuit element is not illustrated in FIG. 1a. Formed above the substrate 101 is an interlayer dielectric 102, which may, for instance, be comprised of silicon dioxide, silicon nitride and the like, and which has formed therein a metal-containing region 103 providing electric contact to one or more circuit elements within the substrate 101. The region 103 may be comprised of tungsten, tungsten silicide or any other appropriate contact metal that is well known in the art. An etch stop layer 104, for instance comprised of silicon nitride, silicon carbide, nitrogen-enriched silicon carbide and the like, may be formed on the interlayer dielectric 102. A capping layer 110 comprised of silicon dioxide is formed on the low-k dielectric layer 106, since the low-k material usually suffers from a reduced hardness and stiffness compared to, for instance, silicon dioxide or silicon nitride. Hence, the capping layer 110 is provided to reduce dishing and erosion effects during a chemical mechanical polishing process performed later on for removing excess metal.
An anti-reflective coating (ARC) layer 105 is located on top of the dielectric layer 106, wherein the ARC layer 105 is comprised of silicon oxynitride. Optical characteristics of the ARC layer 105 are tuned in accordance with the requirements of a subsequent photolithography process to be performed to pattern the ARC layer 105 and the underlying capping layer 110 and the dielectric layer 106. For example, the index of refraction in combination with a thickness of the ARC layer 105 is selected with respect to an exposure wavelength of the subsequent photolithography to reduce back-reflection from a bottom surface 107a of a resist layer 107 that is formed on the ARC layer 105, wherein, according to the required optical resolution of the lithography process, the resist layer 107 is selected for a specified exposure wavelength. As previously discussed, for sophisticated applications, the 248 nm lithography is increasingly being replaced by a 193 nm lithography, so that the resist layer 107 exhibits an enhanced sensitivity in this wavelength range, however, at the price of also exhibiting an increased reactivity with nitrogen and nitrogen compounds. The increased reactivity of the resist layer 107 with nitrogen and nitrogen compounds may degrade the formation of an opening 108, indicated by dashed lines, which is to be formed within the resist layer 107 to form a corresponding trench in the ARC layer 105, the capping layer 110 and the dielectric layer 106.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After the formation of any circuit elements in the substrate 101, the metal-containing region 103 embedded into the interlayer dielectric 102 is formed in accordance with well-established manufacturing processes. For instance, depending on the dimensions of the circuit elements, which the metal-containing region 103 is connected to, a correspondingly designed lithography process has to be used, possibly on the basis of a radiation source with a wavelength of 193 nm. Thereafter, the etch stop layer 104 may be deposited by well-established deposition techniques, such as plasma enhanced chemical vapor deposition (PECVD) with a desired thickness and material composition.
Thereafter, the low-k dielectric layer 106 is formed by means of deposition and/or spin-on techniques as are required by the material composition of the dielectric layer 106. For instance, SiCOH is a frequently used material composition for low-k dielectrics, which may, depending on the microstructure of the material, be deposited by various process recipes. In other cases, the dielectric layer 106 may be formed by spin-on techniques when materials of significantly reduced permittivity are required. Thereafter, the capping layer 110 is deposited by PECVD from TEOS or silane. Then, the ARC layer 105 is formed by well-established PECVD techniques wherein process parameters are controlled such that the desired optical behavior of the ARC layer 105 is obtained. That is, during the deposition, the ratio of nitrogen and oxygen in the ARC layer 105 is adjusted to achieve, in combination with a specified layer thickness, a low back-reflection from the surface 107a at the exposure wavelength under consideration. In some conventional approaches, the ARC layer 105 is formed by spin-on techniques with nitrogen-depleted materials, wherein, however, a poor etch selectivity to the layer 106 may result in subsequent etch processes. Next, the resist layer 107 is formed by spin-on techniques including any appropriate pre-exposure processes.
As is evident from the above description, nitrogen is incorporated in a plurality of layers, such as the etch stop layer 104 and in particular the ARC layer 105, and may also be present in varying amounts in the form of nitrogen, nitrogen compounds and nitrogen radicals in the low-k dielectric layer 106, as these materials are typically present in any processes for forming the layers 104 and/or 106 and/or 105. The nitrogen and corresponding compounds may readily diffuse into the resist layer 107 or the nitrogen may come directly into contact with the resist layer 107 as it represents a considerable amount of the stoichiometric composition of the ARC layer 105. Hence, the nitrogen may interact with the resist material, thereby degrading the sensitivity of the resist with respect to an exposure wavelength to be subsequently used. In particular, a resist designed for a 193 nm exposure wavelength readily reacts with nitrogen and its compounds, thereby deteriorating the non-linear behavior of the resist upon exposure. As a consequence, the dimensions of the opening 108 to be formed within the resist layer 107, as indicated by the number 108b, may not be imaged into the resist layer 107 as precisely as is required for a subsequent patterning of the dielectric layer 106.
FIG. 1b schematically shows the semiconductor device 100 after exposure and development of the resist layer 107 to actually form the opening 108 therein. Due to the degraded optical characteristics of the resist layer 107, resist residue 108a may remain after the development of the resist layer 107, thereby affecting the contour and/or the dimensions of the opening 108. Since the resist layer 107 acts as an etch mask in a subsequent anisotropic etch process, the variation of the contour and/or dimension of the opening 108 also negatively affects the etch process, which may finally lead to a metal trench of reduced reliability.
FIG. 1c schematically shows the semiconductor device 100 after completion of the anisotropic etch process for opening the ARC layer 105, the capping layer 110, the dielectric layer 106 and the etch stop layer 104. A trench 109 having a contour and dimension that may significantly deviate from the target dimension, as indicated by the dashed lines 108b, is formed within the dielectric layer 106.
FIG. 1d schematically illustrates the semiconductor device 100 after depositing a barrier layer 112, filling copper 111 into the trench 109 and removing excess material. The above process sequence may be performed by well-established damascene process flows including the sputter deposition of the barrier layer 112 and a seed layer (not shown), followed by an electrochemical deposition of the copper 111. Thereafter, the excess material of the copper 111 and the barrier layer 112 is removed by chemical mechanical polishing (CMP), wherein also the ARC layer 105 is removed. During the CMP process, the capping layer 110 imparts sufficient mechanical stability to the low-k dielectric layer 106 and also acts as a CMP stop layer. Since the width of the trench 109 may be in the range of 0.1 μm and even significantly less for a semiconductor device of a 90 nm technology, the fluctuation in lateral dimension may result in a copper line of reduced reliability, thereby negatively influencing production yield and thus production costs.
In view of the problems identified above, there is a need for an improved technique enabling the patterning of a low-k dielectric layer without undue resist poisoning and adequate mechanical stability for advanced lithography using an exposure wavelengths of, for example, 248 nm and even less.